1. Field of the Invention
The present invention relates to a plasma display panel (PDP) driving method. More specifically, the present invention relates to a method for driving a PDP with a reduced reset time.
2. Discussion of the Related Art
Recently, liquid crystal displays (LCDs), field emission displays (FEDs), and PDPs have been actively developed. Generally, PDPs may have better luminance and light emission efficiency compared to other types of flat panel display devices, and they may also have wider viewing angles. Therefore, PDPs are receiving attention as substitutes for the conventional cathode ray tubes (CRTs) for displays bigger than 40 inch displays.
A PDP uses plasma, generated via a gas discharge process, to display characters or images, and tens of thousands to millions of pixels may be provided in a matrix format, depending on its size. Depending upon driving voltage waveforms and discharge cell structures, PDPs are typically categorized into direct current (DC) PDPs or alternating current (AC) PDPs.
Since DC PDPs have exposed electrodes in the discharge space, they allow a current to flow in the discharge space while the voltage is supplied, which requires resistors for current restriction. On the other hand, an AC PDPs electrodes are covered by a dielectric layer, and capacitances are naturally formed to restrict the current. Additionally, the dielectric layer protects the electrodes from ion shocks during discharging. Accordingly, AC PDPs have a longer lifespan than DC PDPs.
FIG. 1 shows a perspective view of an AC PDP.
As shown, a pair of a scan electrode 4 and a sustain electrode 5, disposed over a dielectric layer 2 and a protection film 3, are provided in parallel under a first glass substrate 1. A plurality of address electrodes 8, covered with an insulation layer 7, is installed on a second glass substrate 6. Barrier ribs 9, which are parallel to the address electrodes 8, are formed on the insulation layer 7 between the address electrodes 8. Phosphor 10 is formed on the surface of the insulation layer 7 between the barrier ribs 9. The first and second glass substrates 1 and 6, which have a discharge space 11 between them, face each other so that the scan electrode 4 and the sustain electrode 5 pair may cross the address electrodes 8 at right angles. The address electrodes 8, the scan electrode 4 and the sustain electrode 5 pair, and the discharge space 11 form a discharge cell 12.
FIG. 2 shows a PDP electrode arrangement diagram.
As shown in FIG. 2, PDP electrodes are configured in a matrix. Specifically, address electrodes A1 to Am are formed in the column direction, and scan electrodes Y1 to Yn (Y electrodes) and sustain electrodes X1 to Xn (X electrodes) are alternately formed in the row direction. The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG. 1.
FIG. 3 shows a conventional PDP driving waveform diagram.
According to the conventional PDP method shown in FIG. 3, each subfield includes a reset period, an address period, and a sustain period.
The reset period, which includes an erase period, a Y ramp rising period, and a Y ramp falling period, erases wall charge states of a previous sustain, and sets up wall charges in order to stably perform a next address.
In the address period, panel cells to be turned on are selected, and wall charges accumulate to the selected cells (i.e., the addressed cells). In the sustain period, discharges for displaying pictures with the addressed cells is performed.
The wall charges are charges formed on the wall (e.g., a dielectric layer) of the discharge cell near each electrode and accumulate on the electrode. The wall charges do not actually contact the electrode, but they may be described to be “formed,” “accumulated,” and “piled” on the electrode. Also, the wall voltage represents a potential difference formed on the discharge cell wall by the wall charges.
In order to improve the PDP's efficiency, over 10% of Xe may be utilized in the discharge gas, and the discharge firing voltage increases as the rate of Xe increases. Therefore, the voltage at the Y electrode is reduced to the negative voltage in the Y ramp falling period, and the scan pulse applied to the Y electrode is reduced to the negative voltage in the address period.
A discharge in the address period is generated after a time corresponding to an address discharge delay time is passed starting from a time when data pulses are applied to the Y electrode and X electrode. But, when the address discharge delay time is greater than the address time allocated to one scan line, the address discharge fails. Therefore, the cell that is not accurately addressed will not be discharged in the following sustain discharge period, as it should be.
Therefore, as shown in the driving waveform of FIG. 4, the address discharge delay time is reduced by lowering the voltage at the Y electrode to a negative voltage of Vnf in the falling reset period and applying a negative voltage of Vscl which is a scan pulse and is lower than the voltage of Vnf to the Y electrode in the address period. Accordingly, per the driving waveform of FIG. 4, the address discharge delay time may be reduced by applying a negative voltage of Vscl, which is lower than the voltage of Vnf, at the Y electrode after the falling ramp through the scan pulse applied to the Y electrode in the address period.
But when a low negative voltage is applied to the Y electrode, an erroneous sustain discharge may be generated between it and the address electrode of a non-selected cell.